Research projects

Studies sorting when the comparator cannot tell apart values closer than a tolerance δ (the Ajtai et al. model). The project measures output error and performance of dual pivot quicksort, mergesort, shellsort and heapsort for δ ∈ {3, 5, 7, 11}, serial and parallel, using exact counts of inversions and the longest sorted subsequence.

The worst case error of quicksort stays bounded at 3δ while it grows with n for the other three. With δ = 11, serial quicksort runs 5.4% faster and executes 11.9% fewer instructions.

Evaluates 2D convolution, with contiguous and row allocated storage, and blocked matrix multiplication (GEMM) in C, in float and double precision. Each kernel has a complete version and an approximate one that skips kernel positions or iterations of the inner k loop. The study relates time, cycles, instructions, IPC, cache and branch counters to mean absolute error, mean relative error, RMSE and maximum error.

The published campaign covers 276 configurations with 50 repetitions each, run as batch jobs on the group's Saruê server.

Measures how loop perforation and related approximations change the energy consumption of matrix multiplication on a Raspberry Pi Pico 2W. An INA226 current sensor read by an ESP8266 records time and energy for matrices of order 40 to 200, and Python scripts compare the exact and approximate results with error metrics.

Designs a hardware accelerator for matrix multiplication as a systolic array of multiply accumulate (MAC) processing elements, described in Verilog and implemented on a Spartan‑7 FPGA. The accelerator is compared in performance and energy efficiency with a GEMM baseline running on the CPU with OpenBLAS, the kind of workload behind machine learning and image processing.

The first version is a 3 × 3 array of 4 bit processing elements with 10 bit accumulators, verified in simulation, with Vivado builds run as batch jobs on the group's Saruê server.

Characterizes exact adder architectures (ripple carry, carry lookahead, carry skip, carry select, carry save, Kogge Stone and the vendor IP) at 8, 16 and 32 bits. Each design is synthesized and simulated in Vivado under uniform, normal and exponential input distributions to compare LUT and register usage with static, dynamic and total power. These designs are the baseline for the group's approximate adders.

Compares exact multipliers (structural Wallace/Dadda tree, 4:2 compressors and radix 4 Booth) with approximate designs such as partial product perforation, hybrid radix 4 Booth and approximate 4:2 compressors. LUT, DSP and power figures from Vivado are set against MAE, MSE, MRED, NMED and error probability to find the Pareto trade offs between accuracy and cost.