CSER
Research line

Trading accuracy for efficiency

Our work belongs to approximate computing (AxC): designing circuits, systems and programs that insert errors on purpose, in a disciplined and tunable way, to save energy, area or time in applications that tolerate them. For every technique we study, we ask two questions: how much does it save, and how much error does it introduce?

Why approximate

Energy is the limit

With the end of Dennard scaling and the slowdown of Moore's law, each new transistor no longer comes with a free drop in power. Energy has become a first order constraint, from battery powered sensors to data centers.

Demand keeps growing

Machine learning, signal processing and image processing need massive amounts of arithmetic, often under tight latency and power budgets at the edge and in the cloud.

Many applications tolerate error

Approximation is possible because many applications do not need exact answers:

  • human perception cannot notice small changes in images, audio or video;
  • data mining and ranking have no single correct answer;
  • iterative and probabilistic algorithms already converge to approximate results;
  • sensor and signal inputs are noisy to begin with;
  • neural networks often keep their accuracy with reduced precision weights.

Designing an approximate system

  1. Analyze the application to define its quality requirements and error metrics.
  2. Analyze the workload to separate critical computations from approximable ones.
  3. Approximate systematically, using knowledge from more than one layer of the system.
  4. Model the error, so output quality can be estimated without running every configuration.
  5. Explore the design space to choose the best configurations within the quality constraints.
  6. Test under different input distributions, because error depends on the data.

The set of all possible approximation configurations forms the design space. Searching it efficiently is one of the central problems of the field, and the focus of the group's work on metaheuristics.

The abstraction stack

Approximate computing is not a single technique but a range of approaches spread across the design stack, from the circuit to the algorithm.

Hardware
  • Approximate adders and multipliers
  • Reduced voltage and approximate writes in SRAM and DRAM
  • Configurable arithmetic units and voltage overscaling in processors and NPUs
  • Reduced numeric formats: FP16, BF16, INT8, posits
Compilation and synthesis
  • Approximate logic synthesis (AxLS, BLASYS)
  • Loop perforation and approximate memoization
  • Precision scaling
  • Operator fusion and pruning in TVM and XLA
  • Quantization (PTQ and QAT) to INT8 and INT4
Software and algorithms
  • Sampling, task skipping and early exit
  • Pruning of weights and channels
  • Quality of service control over approximable regions
  • Error tolerant domains: image, video, audio, ML inference

Adapted from Leon et al. (2025).

Approximation in practice

Software

Skipping loop iterations

Exact 
for (int i = 0; i < b; i++)
    loop_body();
Approximate 
for (int i = 0; i < b; i += 2)
    loop_body();

Half of the iterations run.

Hardware

Simplifying a full adder

Exact 
S    = A ⊕ B ⊕ Cin
Cout = A·B + Cin·(A ⊕ B)
Approximate 
S    = A ⊕ B
Cout = Cin

The AND and OR gates are removed.

Architecture

Fewer processing cores

Exact
Approximate

16 cores reduced to 9.

Software and hardware

An approximate instruction

Loop 
for (int i = 0; i < b; i = ADDX(i, n))
    loop_body();
Custom ISA 
int ADDX(int i, int n) {
  int r;
  asm volatile("addx %[z], %[x], %[y]"
      : [z] "=r" (r)
      : [x] "r" (i), [y] "r" (n));
  if (r <= i) r = i + n; /* correction */
  return r;
}

An approximate add implemented in the processor, with a correction that keeps the loop moving forward.

Adapted from Catelan (2025).

Our research fronts

The group works mostly at the hardware and compilation levels, with connections to software and to the tools that support the whole flow.

Hardware operators

Approximate adders (LOA, HEAA, HOERAA, HERLOA) and multipliers (4:2 compressors, radix 4 Booth, partial product perforation, DSP based designs) in Verilog for FPGA, characterized by area, power and error. Together they form the group's operator library, in the spirit of EvoApprox8b and SMApproxLib. A squaring circuit and a multiply and accumulate systolic array apply these operators in larger datapaths.

Design space exploration

Metaheuristics (VNS and GRASP) search for the best combination of approximate operators in a Sobel edge detection filter under PSNR or SSIM constraints. Each candidate is evaluated with real synthesis in Vivado instead of an analytical model, so area and power come from implemented designs.

Software and embedded systems

Convolution and matrix multiplication in C with iteration skipping and precision scaling from double to float, which reached speedups of 1.66× in convolution and 1.94× in DGEMM, with errors around 10−7 for the precision change. Loop perforation on microcontrollers measures what those savings mean in real energy on a battery powered device.

Analytical tools

Clang abstract syntax trees are turned into dataflow graphs to model error propagation before synthesis, which cuts the cost of exploring the design space. A second line maps LLVM IR to RISC-V, toward custom ISA extensions with approximate instructions.

How the research fronts connect Design space exploration and hardware operators exchange the operator library and measured results. Hardware operators feed matrix operations and embedded systems, which feed back requirements. Matrix operations inform embedded systems about real energy. Analytical tools support hardware operators, with potential links to design space exploration and matrix operations. operator library measured results speedup toreal energy Design space exploration metaheuristics, optimization Hardware operators adders, multipliers, functions Matrix operations DGEMM, convolution Embedded and IoT energy, loop perforation Analytical tools Clang, RISC-V, error graphs
established dependency potential or future connection

How we measure cost

Software on servers

  • Hardware counters from Linux perf: cycles, instructions, IPC, cache and branch misses.
  • User space events only, split into passes small enough that no counter is multiplexed, so counts are exact rather than estimated.
  • Threads pinned to cores, address space randomization disabled, and many repetitions per configuration, reported with confidence intervals.
  • Package and DRAM energy from Intel RAPL.
  • Long campaigns run as batch jobs with HTCondor on the group's server, so results do not depend on an open session.

Circuits on FPGA

  • Synthesis and implementation in AMD Vivado for a Spartan‑7 device (xc7s50csga324‑1).
  • Area as LUTs, CARRY4 cells, registers and DSP blocks; static, dynamic and total power from the implemented design.
  • Simulation over exhaustive inputs at 8 bits and over uniform, normal and exponential input distributions at 16 and 32 bits.

Embedded devices

  • Current measured with an INA226 sensor, sampled by a second microcontroller so the measurement does not disturb the device under test.
  • Results are sent to a host and compared with the exact computation offline when the device lacks memory to do it.

How we measure error

Every approximate design is evaluated against its exact counterpart on the same inputs. No single number describes error well: an average can hide rare large mistakes, and an absolute value means little without the size of the result. We therefore report several metrics together.

For \(n\) inputs, \(O^{ac}_i\) is the exact (accurate) output and \(O^{ax}_i\) the approximate output for input \(i\). The error distance of one output is \(ED_i = \lvert O^{ac}_i - O^{ax}_i \rvert\).

ED

Error Distance

\[ ED_i = \lvert O^{ac}_i - O^{ax}_i \rvert \]

The error of a single output, the building block of the metrics below.

EP

Error Probability

\[ EP = \frac{1}{n}\sum_{i=1}^{n} \big[\, O^{ac}_i \neq O^{ax}_i \,\big] \]

Fraction of inputs with a wrong result, however small.

MAE

Mean Absolute Error

\[ MAE = \frac{1}{n}\sum_{i=1}^{n} ED_i \]

Average error distance, also called mean error distance (MED).

NMED

Normalized Mean Error Distance

\[ NMED = \frac{MAE}{\max_{i} \lvert O^{ac}_i \rvert} \]

MAE divided by the largest exact output, so designs of different widths can be compared.

WCE

Worst Case Error

\[ WCE = \max_{i} \, ED_i \]

The largest error over all inputs; it exposes rare catastrophic cases that averages hide.

MRED

Mean Relative Error Distance

\[ MRED = \frac{1}{n}\sum_{i=1}^{n} \frac{ED_i}{\lvert O^{ac}_i \rvert}, \quad O^{ac}_i \neq 0 \]

Average error relative to the size of the exact result.

Bias

Mean Relative Signed Error

\[ Bias = \frac{1}{n}\sum_{i=1}^{n} \frac{O^{ac}_i - O^{ax}_i}{\lvert O^{ac}_i \rvert}, \quad O^{ac}_i \neq 0 \]

Like MRED but keeps the sign: a positive bias means the design underestimates on average. Errors that cancel out matter when results are accumulated.

WHD

Worst Case Hamming Distance

\[ WHD = \max_{i} \sum_{j=0}^{b-1} O^{ac}_{i,j} \oplus O^{ax}_{i,j} \]

The largest number of wrong bits in one output, where \(b\) is the output width and \(O_{i,j}\) is bit \(j\) of output \(i\).

MSE

Mean Squared Error

\[ MSE = \frac{1}{n}\sum_{i=1}^{n} \left( O^{ac}_i - O^{ax}_i \right)^2 \]

Penalizes large errors more than small ones; its square root is the RMSE.

PSNR

Peak Signal to Noise Ratio

\[ PSNR = 10 \log_{10} \frac{L^2}{MSE} \]

For images, in decibels; \(L\) is the largest possible pixel value, 255 for 8 bit images. Higher is better.

SSIM

Structural Similarity Index

\[ SSIM = l(ac, ax) \cdot c(ac, ax) \cdot s(ac, ax) \]

For images: the product of the similarity of local luminance \(l\), contrast \(c\) and structure \(s\) between exact and approximate images. 1 means identical.

Comparing designs

A cheaper design with more error is not better or worse by itself. We plot each design by cost (area, power, energy or cycles) against error and keep the Pareto frontier: the designs that no other design beats on both axes at once. A new technique is worth adopting only when it moves that frontier.

Further reading