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Teaching tools · Computer Organization

RISC-V simulators

Five educational simulators that follow the Patterson and Hennessy textbook, RISC-V edition, from how a C program becomes instructions to how many cores share memory. They are used in the Computer Organization course at UFT, run entirely in the browser with nothing to install, and offer Portuguese and English interfaces with a light theme and a high contrast dark theme.

At a glance

SimulatorCoversTextbook
Compilerfrom a subset of C to LLVM IR and RISC-V, SSA, control and data flow, heat maps, classic and approximate optimizationsChapter 2
Arithmeticintegers, IEEE 754 floating point, fixed point, roundingChapter 3
Processorssingle cycle, pipeline, Tomasulo, caches, virtual memoryChapters 4 and 5
Multiprocessingcache coherence (MSI, MESI, MOESI) and atomic instructionsChapters 5 and 6
Data level parallelismvector processor, GPU and TPUChapter 6

Simulators

RISC-V Compiler Simulator

Chapter 2
compilerLLVM IRSSAcalling conventionapproximate computing
Abstract syntax tree of an array sum, with the type of each expression computed by semantic analysis
  • Compiles MiniC, a subset of C with int, float, pointers, arrays and recursion, showing the tokens, the abstract syntax tree growing as the parser builds it and the symbol table with its scopes.
  • Generates LLVM IR as clang -O0 does and then RISC-V assembly, side by side and linked to the source: clicking a line in any of the three views highlights the matching lines in the other two.
  • Draws the activation record of each function, runs the generated code and opens it in the processor simulator to watch it go through the pipeline.
  • For research: mem2reg and SSA form, control flow graphs with dominators and natural loops, per block data flow graphs with the critical path, static and measured heat maps with the cycles of each instruction on the processor models, and classic and approximate optimizations (loop perforation, reduced precision, approximate multiplication) with error versus speedup curves. Graphs export to SVG and Graphviz DOT, data to CSV.
MiniC · LLVM IR · SSA · RV32IMF · ilp32f ABIOpen simulatorSource code →

RISC-V Floating Point Simulator

Chapter 3
arithmeticIEEE 754fixed pointinteger algorithms
The 32 bits of 0.1 in single precision, colored by sign, exponent and fraction, with the value stored and the rounding decision
  • Any number converted bit by bit to double, single, half, bfloat16 and the two 8 bit OCP formats, with the stored value, the error in ULPs and the guard, round and sticky bits.
  • fadd, fmul, fdiv, fsqrt and fmadd shown as the hardware steps, under the five RISC-V rounding modes and stochastic rounding, with the fflags exceptions.
  • Integer multiplication and division in the textbook step tables, fixed point Qm.n formats, experiments on accumulated error and seeded exercise lists with automatic grading.
Every result is first computed exactly with BigInt rationalsOpen simulatorSource code →

RISC-V Processor Simulator

Chapters 4 and 5
processorspipeliningTomasulomemory hierarchy
Pipelined datapath in the style of the textbook, with the hazard detection unit stalling a floating point instruction
  • Runs RV32 and RV64 programs on a single cycle datapath, a five stage pipeline with forwarding, hazard detection and branch prediction, the static dual issue pipeline of section 4.10, and Tomasulo with or without a reorder buffer.
  • Each step explains what happened and lights up the wires and units involved, drawn as the datapath figures of the textbook.
  • Configurable L1, L2 and L3 caches, a TLB with Sv32 and Sv39 page tables and page faults, and execution time compared through the performance equation.
RV32/RV64 IMFD · single cycle · pipeline · dual issue · out of orderOpen simulatorSource code →

RISC-V Multiprocessing Simulator

Chapters 5 and 6
multiprocessingcache coherencesnoopingA extension
MESI state diagram: the accessing core moves from S to M with BusUpgr while another cache goes from S to I
  • Two to four cores with private caches on a snooping bus, under the MSI, MESI and MOESI protocols, with the same sequence compared across the three.
  • Every access animates a system figure (caches, bus and memory) and the protocol state diagram, showing the transition of the accessing core and of the caches that react.
  • RISC-V programs with lr.w, sc.w and AMOs run on all cores, with examples of a race condition, test and set and test and test and set locks, and false sharing.
MSI · MESI · MOESI · RV32I + AOpen simulatorSource code →

RISC-V Data Level Parallelism Simulator

Chapter 6
parallelismvector extensionGPUTPU
GPU block diagram with the warp scheduler, eight SIMD lanes and the memory system, during branch divergence
  • A vector processor for the RISC-V V extension with up to eight lanes, chaining, strip mining, masks, strided and indexed accesses.
  • A SIMT GPU with warps, a scheduler, up to sixteen lanes, branch divergence with a reconvergence stack and memory coalescing.
  • A TPU style systolic array for matrix multiplication, including int8 quantization, a small MLP and convolution through im2col, plus a comparison of the same workload on the three models.
RVV · SIMT · systolic arrayOpen simulatorSource code →

For the classroom

Figures for slides

The current step can be exported as an SVG figure in the textbook style, ready for slides, exams and the editors students already use.

Tables for exams

Step tables, timelines and event tables export to LaTeX, and blank versions turn any run into an exercise.

Shareable runs

A link reopens a program with its configuration, so a whole class can start from the same example.

All five simulators are free software under the GPL 3.0 license. Each one is a set of static files with no build step and no dependencies, published on GitHub Pages.